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agilent hsdl-3603 irda data compliant 4 mbit/s infrared transceiver data sheet applications digital imaging ?digital still cameras ?photo-imaging printers data communication ?notebook computers ?desktop pcs ?wince handheld products ?personal digital assistants ?printers ?auto pcs ?dongles ?set-top box digital imaging ?digital cameras ?photo-imaging printers telecommunication products ?mobile phones ?pagers electronic wallet small industrial and medical instrumentation ?general data collection devices ?patient and pharmaceutical data collection devices ir lans features fully compliant to irda 1.4 fast infrared (fir) from 9.6 kbit/s to 4 mbit/s typical link distance > 1.5 m miniature package ? height: 3.90 mm (3.75 mm without shield) ?width: 9.80 mm (9.3 mm without shield) ?depth: 4.65 mm (4.4 mm without shield) guaranteed temperature performance, -25 to 70 c ?critical parameters are guaranteed over temperature and supply voltage low power consumption ?low shutdown current (10 na typical) ?complete shutdown of txd, rxd, and pin diode withstands >100 mv p-p power supply ripple typically ? cc supply 2.7 to 5.25 volts integrated optional emi shield led stuck-high protection designed to accommodate light loss with cosmetic windows iec 825-class 1 eye safe interface to various super i/o and controller devices description the hsdl-3603 is a low profile infrared transceiver module that provides interface between logic and ir signals for through-air, serial, half-duplex ir data-link. the module is fully compliant to irda date physical layer specifications v1.4 and iec825-class i eye safe. the hsdl-3603 can be shut down completely to achieve very low power consumption. in the shutdown mode, the pin diode will be inactive and thus producing very little photocurrent even under very bright ambient light. such features are ideal for mobile devices that require low power consumption.
2 ordering information part number packaging type package quantity HSDL-3603-007 tape and reel front view 1800 hsdl-3603-208 tape and reel top view 1800 hsdl-3603-207 tape and reel front view 1800 figure 1. hsdl-3603 functional block diagram. functional block diagram pinout 87654321 rear view figure 2a. rear view diagram with shield. marking information the unit is marked with 3603yyww on the shield. 3603 = product name yy = year ww = work week application support information the application engineering group is available to assist you with the application designs associated with the hsdl-3603 infrared transceiver module. you can contact them through your local sales representatives for additional details. figure 2b. rear view diagram without shield. v cc hsdl-3603 cx1 sd/mode (5) cx2 rxd (4) v cc (6) gnd (8) v cc r1 txd (3) led c (2) led a (1) nc (7) optional shield transmitter receiver 87654321 rear view
3 i/o pins configuration table pin symbol description i/o type function 1 led a led anode input this pin can be connected directly to v cc (i.e., without series resistor) at less than 3 v. please refer to table 1 for v cc versus series resistor, r1. 2 led c led cathode output leave this pin unconnected. 3 txd transmit data input, this pin is used to transmit serial data when sd/mode pin is low. if this active high pin is held high longer than ~100 s, the led would be turned off when used in conjunction with the sd/mode pin. txd is low at initialization. 4 rxd receive data output, this pin is capable of driving a standard cmos or ttl load. no external active low pull-up or pull-down resistor is required. it is in tri-state mode when the transceiver is in shutdown mode and during digital serial programming operations. rxd is high at initialization. 5 sd/mode shutdown/ input, the transceiver is in shutdown mode if this pin is high for more than mode select active high 400 s. on the falling edge of this signal, the state of the txd pin sampled and used to set receiver low bandwidth (txd=low) or high bandwidth (txd=high) mode. see figure 3 and figure 4 for bandwidth selection timings. sd is low at initialization. 6v cc supply supply regulated, 2.7 to 5.25 volts. voltage voltage 7 nc no connect no connect 8 gnd ground ground connect to system ground. shield emi shield emi shield connect to system ground via a low inductance trace. for best performance, do not connect directly to the transceiver pin gnd. recommended application circuit components component recommended value notes r1 0 ? 5%, 0.5 watt, for 2.7 v 1.8 ? 5%, 0.5 watt, for 3.0 v 4.7 ? 5%, 0.5 watt, for 3.3 v 6.8 ? 5%, 0.5 watt, for 3.5 v cx1 0.47 f 20%, x7r ceramic 1 cx2 6.8 f 20%, tantalum 2 notes: 1. cx1 must be placed within 0.7 cm of the hsdl-3603 to obtain optimum noise immunity. 2. in environments with noisy power supplies, supply rejection performance can be enhanced by including cx2, as shown in figure 1: ?sdl-3603 functional block diagram?on page 2.
4 bandwidth selection timing the transceiver is in default sir/ mir mode when powered on. user needs to apply the following programming sequence to both the sd and txd inputs to enable the transceiver to operate at fir mode. figure 3. bandwidth selection timing at sir/mir mode. figure 4. bandwidth selection timing at fir mode. setting the transceiver to sir/mir mode (9.6 kb/s to 1.152 mbit/s) 1. set sd/mode input to logic high 2. txd input should remain at logic low 3. after waiting for t s 25 ns, set sd/mode to logic low, the high to low negative edge transition will determine the receiver bandwidth 4. ensure that txd input remains low for t h 100 ns, the receiver is now in sir/mir mode 5. sd input pulse width for mode selection should be > 50 ns. v ih 50% t s t h v il 50% 50% txd sd/mode v il v ih 50% t s t h v il 50% 50% txd sd/mode v ih v il setting the transceiver to fir (4.0 mbit/s) mode 1. set sd/mode input to logic high 2. after sd/mode input remains high at > 25ns, set txd input to logic high, wait t s 25 ns (from 50% of txd rising edge till 50% of sd falling edge) 3. then set sd/mode to logic low, the high to low negative edge transition will determine the receiver bandwidth 4. after waiting for t h 100ns, set the txd input to logic low 5. sd input pulse width mode selection should be > 50ns.
5 transceiver i/o truth table inputs outputs txd light input to receiver sd led rxd notes high - low on not valid low high low off low 1, 2 low low low off high don? care - high off high notes: 1. in-band irda signals and data rates 4mbit/s. 2. rxd logic low is a pulsed response. the condition is maintained for a duration dependent on pattern and strength of the incid ent intensity. caution: the bicmos inherent to the design of this component increases the component? suscepti- bility to damage from electrostatic discharge (esd). it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation, which may be induced by esd.
6 recommended operating conditions parameter symbol min. typ. max. units conditions operating temperature t a ?5 70 c supply voltage v cc 2.7 5.25 v logic input voltage logic high v ih 2/3 v cc v cc v for txd, sd/mode logic low v il 0 1/3 v cc v receiver input logic high ei h 0.0036 500 mw/cm 2 for in-band signals 115.2 kbit/s [4] irradiance 0.0090 500 mw/cm 2 0.576 mbit/s in-band signals 4 mbit/s [4] logic low ei l 0.3 w/cm 2 for in-band signals 115.2 kbit/s [4] led (logic high) current i leda 400 600 ma pulse amplitude receiver data rate 0.0096 4.0 mbit/s note: 4. an in-band optical signal is a pulse/sequence where the peak wavelength, p, is defined as 850 p 900 nm, and the pulse characteristics are compliant with the irda serial infrared physical layer link specification v1.4. absolute maximum ratings for implementations where case to ambient thermal resistance is 50 c/w. parameter symbol min. max. units notes storage temperature t s ?0 100 c operating temperature t a ?5 70 c led anode voltage v leda 0 6.5 v supply voltage v cc 0 6.5 v input voltage: txd, sd/mode v i 0 6.5 v output voltage: rxd v o 0 6.5 v dc led transmit current i led (dc) 150 ma average transmit current i led (pk) 650 ma 3 note: 3. 25% duty cycle, 90 s pulse width.
7 electrical and optical specifications specifications (min. and max. values) hold over the recommended operating conditions unless otherwise noted. unspecified test conditions may be anywhere in their operating range. all typical values (typ.) are at 25 c with v cc set to 3.0 v unless otherwise noted. parameter symbol min. typ. max. units conditions receiver viewing angle 2 30 peak sensitivity wavelength p 880 nm rxd output voltage logic high v oh v cc ?0.2 v cc vi oh = ?00 a, ei 0.3 w/cm 2 logic low v ol 0 0.4 v i ol = 200 a, ei 3.6 w/cm 2 rxd pulse width (sir) t pw (sir) 1 4.0 s 15 , c l = 12 pf [5] rxd pulse width (mir) t pw (mir) 100 500 ns 15 , c l = 12 pf 6] rxd pulse width (fir) t pw (fir) 80 165 ns 15 , c l = 12 pf [7] rxd rise and fall times t r , t f 25 ns c l =12 pf receiver latency time t l 10 150 s receiver wake up time t rw 10 150 s transmitter radiant intensity ie h 100 180 mw/sr i leda = 400 ma, 15 , v txd v ih t = 25 c viewing angle 2 30 60 peak wavelength p 875 nm spectral line half width ? 35 nm txd logic levels high v ih 2/3 v cc v cc v low v il 0 1/3 v cc v txd input current high i h 0.02 10 av i v ih low i l 10 ?.02 10 a0 v i v il led current on i vled 400 600 ma v i (txd) v ih shutdown i vled 20 1000 na v i (sd) v ih , t a = 25 c txd pulse width (sir) t pw (sir) 1.5 1.6 1.8 st pw (txd) = 1.6 s at 115.2 kbit/s txd pulse width (mir) t pw (mir) 148 217 260 ns t pw (txd) = 217 ns at 1.152 mbit/s txd pulse width (fir) t pw (fir) 115 125 135 ns t pw (txd) = 125 ns at 4.0 mbit/s maximum optical pw t pw(max.) 60 100 s txd rise and fall time (optical) t r , t f 40 ns t pw (txd) = 125 ns at 4.0 mbit/s transceiver supply current shutdown i cc1 10 1000 na v sd 2/3 v cc , t a = 25 c idle i cc2 1.8 3.0 ma v i (txd) v il , ei = 0 active i cc3 2.5 ma ei = 10 mw/cm 2 notes: 5. for in-band signals 115.2 kbit/s where 3.6 w/cm 2 ei 500 mw/cm 2 . 6. for in-band signals at 1.152 mbit/s where 9.0 w/cm 2 ei 500 mw/cm 2 . 7. for in-band signals of 125 ns pulse width, 4 mbit/s, 4 ppm at recommended 400 ma drive current.
8 figure 5. ir lop vs. iled. figure 7. rxd output waveform. figure 8. led optical waveform. figure 9. txd ?tuck on?waveform. figure 10. receiver wakeup time waveform. figure 11. txd wakeup time waveform. t f v oh 90% 50% 10% v ol t pw t r t f led off 90% 50% 10% led on t pw t r t pw (max.) txd led rx light t rw rxd sd tx light t tw txd sd ie h (mw/sr) 390 iled (ma) 210 300 150 250 650 330 290 170 500 250 350 350 400 450 550 600 radiant intensity (mw/sr) vs. iled t a = 25?, v cc = 3.0 v, on-axis 190 230 270 310 370 figure 6. ir vled vs. iled. vled_a (v) 2.80 iled (ma) 2.20 300 2.00 250 650 2.60 500 2.30 350 400 450 550 600 vled_a vs. iled t a = 25 c, v cc = 3.0 v 2.10 2.40 2.50 2.70
9 figure 12. package outline dimensions. hsdl-3603 package outline dimensions (with shield) unit: mm tolerance: 0.2 mm 4.65 4.10 9.80 3.90 1.00 4.90 mounting center 0.1 0.37 0.83 0.10 +0.20 93 1 3.85 0.95 0.75 0.25 1.70 p1.0 x 7 = 7 7 6 5 4 3 2 0.65 3.5 1 leda 5 sd/mode 2 ledc 6 vcc 3 txd 7 nc 4 rxd 8 gnd light receiving center 81 emitting center
10 hsdl-3603 tape and reel dimensions (with shield) figure 13. tape and reel dimensions. 16.40 + 2.00 0 b c 2.00 0.50 3.46 8.00 0.10 4.00 0.10 16.00 0.30 1.75 0.10 1.55 0.05 0.30 0.10 4.50 0.10 polarity parts mounted leader (40 mm min.) empty (40 mm min.) 0.75 0.10 progressive direction "b" "c" quantity pin 8: gnd pin 1: led a +0.10 0 3.30 +0.10 0 7.50 0.10 label detail a 330 80 1800 9.50 0.10 5 (max.) 4.65 0.10 5.15 0.10 5 (max.) material of carrier tape: conductive polystyrene material of cover tape: pvc method of cover: heat activated adhesive unit: mm empty (40 mm min.) 2.46 0.10 21 0.8 dia. 13.0 0.5 2.0 0.5 r 1.0 detail a
11 figure 14. package outline dimensions. hsdl-3603 package outline dimensions (without shield) 4.40 3.58 9.30 3.75 2.70 0.75 9.30 0.65 (8 places) light receiving center emitting center 2.93 0.55 3.75 0.83 (2 places) pitch 1.00
12 hsdl-3603 tape and reel dimensions (without shield) figure 15. tape and reel dimensions. 16.40 + 2.00 0 b c 2.00 0.50 3.46 8.00 0.10 4.00 0.10 16.00 0.30 1.75 0.10 1.55 0.05 0.30 0.10 4.50 0.10 polarity parts mounted leader (40 mm min.) empty (40 mm min.) 0.75 0.10 progressive direction "b" "c" quantity pin 8: gnd pin 1: led a +0.10 0 3.30 +0.10 0 7.50 0.10 label detail a 330 80 1800 9.50 0.10 5 (max.) 4.65 0.10 5.15 0.10 5 (max.) material of carrier tape: conductive polystyrene material of cover tape: pvc method of cover: heat activated adhesive unit: mm empty (40 mm min.) 2.46 0.10 21 0.8 dia. 13.0 0.5 2.0 0.5 r 1.0 detail a
13 moisture proof packaging all hsdl-3603 options are shipped in moisture proof package. once opened, moisture absorption begins. this part is compliant to jedec level 4. baking conditions if the parts are not stored in dry conditions, they must be baked before reflow to prevent damage to the parts. package temperature time in reels 60?c 48 hours in bulk 100?c 4 hours 125?c 2 hours 150?c 1 hour baking should only be done once. figure 16. baking conditions. recommended storage conditions storage 10 c to 30 c temperature relative humidity below 60% rh time from unsealing to soldering after removal from the bag, the parts should be soldered within three days if stored at the recommended storage conditions. if times longer than three days are needed, the parts must be stored in a dry box. units in a sealed moisture-proof package package is opened (unsealed) environment less than 30 c, and less than 60% rh package is opened less than 72 hours perform recommended baking conditions no baking is necessary yes no no yes
14 reflow profile the reflow profile is a straight- line representation of a nominal temperature profile for a convec- tive reflow solder process. the temperature profile is divided into four process zones, each with different ? t/ ? time tempera- ture change rates. the ? t/ ? time rates are detailed in the following table. the temperatures are mea- sured at the component to printed circuit board connections. in process zone p1 , the pc board and hsdl-3603 castellation i/o pins are heated to a temperature of 125 c to activate the flux in the solder paste. the temperature ramp up rate, r1, is limited to 4 c per second to allow for even heating of both the pc board and hsdl-3603 castellation i/o pins. process zone p2 should be of sufficient time duration (> 60 seconds) to dry the solder paste. the temperature is raised to a level just below the liquidus point of the solder, usually 170 c (338 f). process zone p3 is the solder reflow zone. in zone p3, the temperature is quickly raised above the liquidus point of solder to 230 c (446 f) for optimum results. the dwell time above the liquidus point of solder should be between 15 and 90 seconds. it usually takes about 15 seconds to assure proper coalescing of the solder balls into liquid solder and the formation of good solder 0 t-time (seconds) t temperature ( c) 200 170 125 100 50 50 150 100 200 250 300 150 183 230 p1 heat up p2 solder paste dry p3 solder reflow p4 cool down 25 r1 r2 r3 r4 r5 90 sec. max. above 183 c max. 245 c maximum process zone symbol ? t ? t/ ? time heat up p1, r1 25?c to 125?c 4?c/s solder paste dry p2, r2 125?c to 170?c 0.5?c/s solder reflow p3, r3 170?c to 230?c (245?c max.) 4?c/s p3, r4 230?c to 170?c ??c/s cool down p4, r5 170?c to 25?c ??c/s connections. beyond a dwell time of 90 seconds, the intermetallic growth within the solder connec- tions becomes excessive, resulting in the formation of weak and unreliable connections. the temperature is then rapidly reduced to a point below the solidus temperature of the solder, usually 170 c (338 f), to allow the solder within the connections to freeze solid. process zone p4 is the cool down after solder freeze. the cool down rate, r5, from the liquidus point of the solder to 25 c (77 f) should not exceed -3 c per second maximum. this limitation is necessary to allow the pc board and hsdl-3603 castellation i/o pins to change dimensions evenly, putting minimal stresses on the hsdl-3603 transceiver. figure 17. reflow graph.
15 dimension mm inches a 2.00 0.079 b 0.70 0.028 c (pitch) 1.00 0.039 d 2.50 0.098 e 1.51 0.059 f 3.09 0.122 g 2.84 0.112 appendix a: hsdl-3603 smt assembly application note 1.0. solder pad, mask, and metal solder stencil aperture figure 18. stencil and pcba. 1.1. recommended land pattern for hsdl-3603 figure 19. top view of land pattern. metal stencil for solder paste printing land pattern pcba stencil aperture solder mask b d a e c shield's solder pad fiducial f g rx lens tx lens 8x solder pad
16 adjacent land keep-out is the maximum space occupied by the unit relative to the land pattern. there should be no other smd components within this area. h ?is the minimum solder resist strip width required to avoid solder bridging adjacent pads. it is recommended that 2 fiducial cross be placed at mid-length of the pads for unit alignment. note: wet/liquid photo- imagineable solder resist/mask is recommended. 1.2. adjacent land keep-out and solder mask areas figure 20. pcba ?adjacent land keep-out and solder mask. dimension mm inches h min. 0.2 min. 0.008 j 10.8 0.425 k 5.1 0.201 l 3.2 0.126 h l tx lens rx lens j solder mask land k y center
17 figure 21. solder paste stencil aperture. see figure 18 t, nominal stencil thickness l, length of aperture mm inches mm inches 0.152 0.006 2.0 0.05 0.12 0.002 0.127 0.005 2.0 0.05 0.15 0.002 w, the width of aperture is fixed at 0.70 mm (0.027 inches) aperture opening for shield pad is 2.50 mm x 1.51 mm as per land dimension. 1.3. recommended metal solder stencil aperture it is recommended that only 0.152 mm (0.006 inches) or 0.127 mm (0.005 inches) thick stencil be used for solder paste printing. this is to ensure ad- equate printed solder paste vol- ume and no shorting. the following combination of metal stencil aperture and metal stencil thickness should be used: apertures as per land dimensions l w t (stencil thickness) solder paste metal stencil
18 dimension mm inches a 2.00 0.079 b 0.70 0.028 c (pitch) 1.00 0.039 appendix b: hsdl-3603 smt assembly application note (no shield) 1.0. solder pad, mask, and metal solder stencil aperture figure 22. stencil and pcba. 1.1. recommended land pattern for hsdl-3603 figure 23. top view of land pattern. metal stencil for solder paste printing land pattern pcba stencil aperture solder mask b a c fiducial rx lens tx lens 8x solder pad
19 adjacent land keep-out is the maximum space occupied by the unit relative to the land pattern. there should be no other smd components within this area. h is the minimum solder resist strip width required to avoid solder bridging adjacent pads. it is recommended that 2 fiducial cross be placed at mid-length of the pads for unit alignment. note: wet/liquid photo- imagineable solder resist/mask is recommended. 1.2. adjacent land keep-out and solder mask areas figure 24. pcba ?adjacent land keep-out and solder mask. dimension mm inches h min. 0.2 min. 0.008 j 10.8 0.425 k 5.1 0.201 l 3.2 0.126 h l tx lens rx lens j solder mask land k
20 figure 25. solder paste stencil aperture. see figure 18 t, nominal stencil thickness l, length of aperture mm inches mm inches 0.152 0.006 2.0 0.05 0.12 0.002 0.127 0.005 2.0 0.05 0.15 0.002 w, the width of aperture is fixed at 0.70 mm (0.027 inches) aperture opening for shield pad is 2.50 mm x 1.51 mm as per land dimension. 1.3. recommended metal solder stencil aperture it is recommended that only 0.152 mm (0.006 inches) or 0.127 mm (0.005 inches) thick stencil be used for solder paste printing. this is to ensure ad- equate printed solder paste vol- ume and no shorting. the following combination of metal stencil aperture and metal stencil thickness should be used: apertures as per land dimensions l w t (stencil thickness) solder paste metal stencil
21 appendix c: pcb layout suggestion the following pcb layout guide- lines should be followed to obtain a good psrr and em immunity, resulting in good electrical performance. things to note: 1. the agnd pin should be connected to the ground plane. 2. c1 and c2 are optional supply filter capacitors; they may be left out if a clean power supply is used. 3. vled can be connected to either unfiltered or unregulated power supply. if vled and v cc share the same power supply and c1 is used, the connection should be before the current limiting resistor r1. in a noisy environ- ment, including capacitor c2 can enhance supply rejection. c1 is generally a ceramic capacitor of low inductance providing a wide frequency response while c2 is a tantalum capacitor of big volume and fast frequency response. the use of a tantalum capacitor is more critical on the v led line, which carries a high current. 4. preferably, a multi-layered board should be used to provide sufficient ground plane. use the layer underneath and near the transceiver module as v cc , and sandwich that layer between ground connected board layers. refer to the diagram below for an example of a 4-layer board. top layer connect the metal shield and module ground pin to bottom ground layer. layer 2 critical ground plane zone. do not connect directly to the module ground pin. layer 3 keep data bus away from critical ground plane zone. bottom layer (gnd) the area underneath the module at the second layer, and 3 cm in all directions around the module, is defined as the critical ground plane zone. the ground plane should be maximized in this zone. refer to application note an1114 or the agilent irda data link design guide for details. the layout below is based on a 2-layer pcb. 28 mm top layer figure 26. pcb layout suggestion. bottom layer 17.2 mm
22 appendix d: general application guide for the hsdl-3603 infrared irda ? compliant 4 mb/s transceiver description the hsdl-3603 wide voltage operating range infrared trans- ceiver is a low-cost and small form factor that is designed to address the mobile computing market such as notebooks, print- ers, and lan access as well as small embedded mobile products such as digital cameras, cellular phones, and pdas. it is fully com- pliant to irda 1.4 specification up to 4 mb/s. the design of the hsdl-3603 also includes the following unique features: low passive component count. shutdown mode for low power consumption requirement. single-receive output for all data rates. selection of resistor r1 resistor r1 should be selected to provide the appropriate peak pulse led current over different ranges of v cc . the recommended selection of r1 is tabulated in the table on page 3. the hsdl-3603 typically provides 180 mw/sr of intensity at the recommended minimum peak pulse led current of 400 ma. interface to recommended i/o chips the hsdl-3603 s txd data input is buffered to allow for cmos drive levels. no peaking circuit or capacitor is required. data rate from 9.6 kb/s up to 4 mb/s is available at the rxd pin. following shows the interface of hsdl-3603 with national semiconductor s super i/os, and the smc i/o chips.
23 irtx irrx1 irsl0 pc87391/2/3/3f-vjg 70 69 68 pc97338vjg 63 65 66 pc87360/3/4/5/6 57 59 58 pc87309vlj 44 43 100 pc8(9)7307 81 80 79 pc8(9)7317vul 81 80 79 please refer to the national semiconductor data sheets and application notes for updated information. (a) national semiconductor super i/o and infrared controller for national semiconductor super i/o and infrared controller chips, ir link can be realized with the following connections: connect irtx of the national super i/o or ir controller to txd (pin 3) of the hsdl-3603. connect irrx1 of the national super i/o or ir controller to rxd (pin 4) of the hsdl-3603. connect irsl0 of the national super i/o or ir controller to sd/mode (pin 5) of the hsdl- 3603. please refer to the table below for the ir pin assignments for the national super i/o and ir con- trollers that support irda 1.4 up to 4 mb/s: figure 27. ns super i/o configuration circuit. txd (3) rxd (4) sd/mode (5) gnd (8) v cc leda (1) r1 v cc sp hsdl-3603 cx1 cx2 national semiconductor super i/o or ir controller irtx irrx1 irsl0 hsdl-3603 functional block diagram ledc (2) v cc (6)
24 figure 28. smc super i/o configuration circuit. irtx irrx irmode fdc37c669fr 89 88 23 fdc37n769 87 86 21 fdc37c957/8fr 204 203 145 or 190 (b) standard micro system corpora- tion (smc) super and ultra i/o controllers for smc super and ultra i/o controller chips, ir link can be realized with the following connections: connect irtx of the smc super or ultra i/o controller to txd (pin 3) of the hsdl-3603. connect irrx of the smc super or ultra i/o controller to rxd (pin 4) of the hsdl-3603. connect irmode of the super or ultra i/o controller to sd/mode (pin 5) of the hsdl- 3603. please refer to the table below for the ir pin assignments for the smc super or ultra i/o control- lers that support irda 1.4 up to 4 mb/s: txd (3) rxd (4) sd/mode (5) gnd (8) gnd v cc leda (1) r1 v cc sp hsdl-3603 cx1 cx2 standard microsystem corporation super i/o or ir controller irrx irmode irtx v cc (6) ledc (2)
25 figure 29. ir layout in mobile phone platform. figure 30. ir layout in pda platform. (c) mobile phone and pda platform the block diagrams below show how the irda port fits into a mobile phone and pda platform. transceiver mod/ de-modulator speaker rf interface audio interface user interface microcontroller dsp core asic controller ir microphone pcmcia controller cpu for embedded application ir ram rom touch panel lcd panel rs232c driver com port
26 appendix e: window design optical port dimensions for hsdl- 3603: to ensure irda compliance, some constraints on the height and width of the window exist. the minimum dimensions ensure that the irda cone angles are met without vignetting. the maximum dimensions minimize the effects of stray light. the minimum size corresponds to a cone angle of 30 and the maximum size corre- sponds to a cone angle of 60 . in the figure below, x is the width of the window, y is the height of the window and z is the distance from the hsdl-3603 to the back of the window. the distance from the center of the led lens to the center of the photodiode lens, k, is 7.08 mm. the equations for computing the window dimen- sions are as follows: x = k + 2 * (z + d) * tana y = 2 * (z + d) * tana the above equations assume that the thickness of the window is negligible compared to the dis- tance of the module from the back of the window (z). if they are com- parable, z' replaces z in the above equation. z' is defined as z' = z + t/n where t is the thickness of the window and n is the refractive index of the window material. the depth of the led image in- side the hsdl-3603, d, is 8 mm. a is the required half angle for viewing. for irda compliance, the minimum is 15 and the maxi- mum is 30 . assuming the thick- ness of the window to be negligible, the equations result in the following tables and graphs: d z k a ir transparent window opaque material opaque material ir transparent window x y figure 31. window design diagram.
27 aperture width aperture height (x, mm) (y, mm) module depth, (z) mm max. min. max. min. 0 16.318 11.367 9.238 4.287 1 17.472 11.903 10.392 4.823 2 18.627 12.439 11.547 5.359 3 19.782 12.975 12.702 5.895 4 20.936 13.511 13.856 6.431 5 22.091 14.047 15.011 6.967 6 23.246 14.583 16.166 7.503 7 24.401 15.118 17.321 8.038 8 25.555 15.654 18.475 8.574 9 26.710 16.190 19.630 9.110 aperture width (x) mm 30 module depth (z) mm 10 47 0 09 15 26 20 5 135 8 aperture width (x) vs. module depth x max. x min. 25 aperture height (y) mm 25 module depth (z) mm 20 47 0 09 26 10 135 8 aperture height (y) vs. module depth 15 5 y max. y min. figure 32. aperture width (x) vs. module depth. figure 33. aperture height (y) vs. module depth.
window material almost any plastic material will work as a window material. polycarbonate is recommended. the surface finish of the plastic should be smooth, without any texture. an ir filter dye may be used in the window to make it look black to the eye, but the total optical loss of the window should be 10% or less for best optical performance. light loss should be measured at 875 nm. the recommended plastic materials for use as a cosmetic window are available from general electric plastics. recommended plastic materials: material light haze refractive number transmission index lexan 141l 88% 1% 1.586 lexan 920a 85% 1% 1.586 lexan 940a 85% 1% 1.586 note: 920a and 940a are more flame retardant than 141l. recommended dye: violet #21051 (ir transmissant above 625 nm). curved front and back (second choice) flat window (first choice) curved front, flat back (do not use) shape of the window from an optics standpoint, the window should be flat. this ensures that the window will not alter either the radiation pattern of the led, or the receive pattern of the photodiode. if the window must be curved for mechanical or industrial design reasons, place the same curve on the back side of the window that has an identical radius as the front side. while this will not completely eliminate the lens effect of the front curved surface, it will significantly reduce the effects. the amount of change in the radiation pattern is dependent upon the material chosen for the window, the radius of the front and back curves, and the distance from the back surface to the transceiver. once these items are known, a lens design can be made which will eliminate the effect of the front surface curve. the following drawings show the effects of a curved window on the radiation pattern. in all cases, the center thickness of the window is 1.5 mm, the window is made of polycarbonate plastic, and the distance from the transceiver to the back surface of the window is 3 mm. figure 34. window design choices. 28
www.agilent.com/semiconductors for product information and a complete list of distributors, please go to our web site. for technical assistance call: americas/canada: +1 (800) 235-0312 or (408) 654-8675 europe: +49 (0) 6441 92460 china: 10800 650 0017 hong kong: (+65) 6271 2451 india, australia, new zealand: (+65) 6271 2394 japan: (+81 3) 3335-8152(domestic/interna- tional), or 0120-61-1280(domestic only) korea: (+65) 6271 2194 malaysia, singapore: (+65) 6271 2054 taiwan: (+65) 6271 2654 data subject to change. copyright ?2003 agilent technologies, inc. obsoletes 5988-7926en december 9, 2003 5988-8659en

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